1. Field of Invention
This invention is directed to a method of chemical mechanical polishing and more particularly for planarizing shallow trench isolation or similar structures for integrated circuits.
2. Description of Related Art
Shallow trench isolation (STI) structures are formed between field effect transistors in an integrated circuit to prevent carriers such as electrons from drifting between adjacent device elements. The fabrication of STI structures involves photolithography to form the trench structures followed by filling of the trenches with insulators. Planarization of the filled trenches is usually accomplished by chemical mechanical polishing (CMP). The CMP process uses chemical etchants and abrasives in the form of aqueous slurries to polish the preliminary STI structures. The CMP process is not without throughput issues with larger diameter wafers or defect concerns such as shallow dishes from overpolishing, microscratches or across the wafer non-uniformity. The importance of overcoming some of the deficiencies or cost factors is evidenced by the technology developments directed to the subject as noted in the patent literature.
U.S. Pat. No. 6,365,520 (Rhoades et al) comprises CMP slurry for planarization of STI based on a mixture of two ranges of particle sizes.
U.S. Pat. No. 6,261,158 (Holland et al ) describes a two step CMP process for planarizing metal interconnects with the imposition of a cleansing/neutralization step as intermediate between stages of CMP.
U.S. Pat. No. 6,234,877 (Koos et al) provides a method of controlling the pH of the slurry composition by an intermediate cleansing rinse of the polishing pads with a diluting solution or a buffered solution.
U.S. Pat. No. 6,207,535 (Lee et al) teaches the thermal hardening of a portion of a third oxide layer prior to CMP of that layer in a STI fabrication process.
U.S. Pat. No. 6,190,999 (Hung et al) relates to a STI structure formed by a sequence of film depositions and the intermediate removal of the silicon nitride hard masking layer to expose the pad oxide layer. An insulating layer is formed over the trench; the pad oxide layer then acts as a polishing stop for planarizing the insulating layer.
U.S. Pat. No. 6,143,662 (Rhoades et al) describes for STI planarization a method of using a CMP slurry mixture of abrasive particles having a mean diameter of between 2 and 30 nm and larger abrasive particles having a mean diameter between 2 and 10 times the mean diameter of the small abrasive particles.
U.S. Pat. No. 6,117,748 (Lou et al) describes a dishing-free process for STI consisting of a two-step CMP with an oxide slurry followed by a poly slurry that stops at the surface of the nitride layer.
U.S. Pat. No. 5,652,177 (Pan) encompasses the sequences of forming a field isolation region by depositing an insulating layer, a polysilicon layer, and a nitride layer over a substrate followed by the lithographic patterning and etching of the silicon and nitride layers over the insulating layer. The nitride layer is removed prior to CMP and the polysilicon layer acts as a polishing stop.